Electrical Engineer II-Firmware Verification

Job Summary

The Electrical Engineer II is responsible for a specific technical activity and completion of assigned tasks on time and budget, with a primary focus on firmware and FPGA verification supporting Leonardo DRS programs. Design, develop, execute, and document verification environments, test plans, and testbenches to validate digital hardware and embedded firmware designs prior to integration. Apply modern verification methodologies and tools — including UVM (Universal Verification Methodology), SystemVerilog, to ensure design intent is met and defects are identified early in the development lifecycle. Use computer-aided engineering and verification software in the performance of assignments.

Job Responsibilities

• Responsible for firmware and FPGA verification activities and completion of assigned tasks on time and budget
• Develop, execute, and maintain verification environments, testbenches, and test plans for digital hardware and firmware designs, documenting and reporting results
• Apply modern verification methodologies and tools (e.g., UVM, SystemVerilog, Python/cocotb, formal verification) to validate design functionality against requirements 
• Develop and execute functional and code coverage models to measure verification completeness and identify gaps
• Review customer specifications and requirements, and under direction, develop verification approaches to best support them, including cost and schedule as key variables
• Develop prototypes, testbenches, and simulation models to retire key development risks 
• Communicate clearly (written and oral) with other company personnel and the customer as required
• May provide technical knowledge and assistance to other engineers and support personnel on verification methodologies and tools

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent combination of education and experience
• 2 years of experience in digital design, FPGA development, or firmware/hardware verification; relevant internship, co-op, or academic project experience is applicable
• Foundational knowledge of digital logic design and verification concepts
• Coursework or hands-on exposure to Hardware Description Languages (VHDL, Verilog, or SystemVerilog)
• Familiarity with modern firmware/FPGA verification methodologies and tools, such as UVM (Universal Verification Methodology), SystemVerilog-based testbenches, Python-based verification frameworks (e.g., cocotb), or formal verification tools 
• Basic understanding of the FPGA/ASIC development flow (simulation, synthesis, timing closure)
• Ability to work independently and collaboratively within a team environment 
• Strong analytical, problem-solving, and debugging skills
• Experience with SystemVerilog Assertions (SVA) and functional/code coverage-driven verification 
• Exposure to formal verification tools (e.g., Cadence JasperGold, Siemens Questa Formal, or similar)
• Familiarity with version control (Git) and continuous integration/regression frameworks for verification
• Experience with FPGA vendor toolchains (Xilinx Vivado, Intel/Altera Quartus) and HDL simulators (Questa/ModelSim, VCS, Xcelium)